Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 μm MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of the prior art MOSFETs consists of a very thin vertical Si layer (FIN) for the channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
FIN MOSFETs offer potential benefits in performance as compared with conventional MOSFETs; See, for example, X. Huang, et al., IEDM Tech. Dig. 1999, p.67. However, in prior art FIN MOSFETs, the gate conductor is not self-aligned to the source/drain diffusion junctions or the channel regions. Therefore, there will be a large series resistance between the channel and the heavily doped source/drain diffusion junctions.
To date, there are no adequate means for fabricating double-gated FIN MOSFET structures in which the gate is self-aligned to the source/drain diffusion junctions and the channels. Thus, there is a continued need for developing a new and improved method of fabricating double-gated FIN MOSFETs in which such self-alignment between the gate and the source/drain diffusion junctions and channels is achieved.